1. Field of the Invention
This invention relates to a level shifter circuit which switches the amount of an output voltage to be output and to a semiconductor memory device including such a level shifter circuit in a row decoder circuit.
2. Description of the Related Art
Conventionally, an electrically rewritable EEPROM is known as one of the semiconductor memory devices. In particular, a NAND cell-type EEPROM in which each NAND cell block includes a plurality of memory cells connected in series is attracting attention as a device that can achieve a high degree of integration.
Each memory cell of a NAND cell-type EEPROM has a FET-MOS structure in which a floating gate (charge storage layer) and a control gate are stacked via an insulating film on a semiconductor substrate. A plurality of memory cells are connected in series, with adjacent cells sharing source/drain, to form a NAND cell. The NAND cell is connected to a bit line as a unit. Such NAND cells arranged in a matrix form a memory cell array. The memory cell array is integrally formed in a p-type semiconductor substrate or in a p-type well.
Each drain positioned at one end of the NAND cells connected in series in a column direction of the memory cell array is commonly connected via a select gate transistor to a bit line, while each source positioned at the other end is also connected via a select gate transistor to a common source line. The control gate of the memory transistor and the gate electrode of the select gate transistor are commonly connected as a control gate line (word line) and a select gate line, respectively, in the row direction of the memory cell array.
This NAND cell-type EEPROM operates as follows. Data programming operations mainly start from a memory cell which is the most remote from the bit line contact. First, when the data programming operation starts, according to write data, the bit line is given 0 V (for “0” data programming bit line) or a power supply voltage Vcc (for “1” data programming bit line), and the select gate line on the selected bit-line contact side is given Vcc. In this case, in the selected NAND cell connected to the “0” data programming bit line, its channel portion is fixed to 0 V via a select gate transistor. In the selected NAND cell connected to the “1” data programming bit line, on the other hand, its channel portion is charged via the select gate transistor up to [Vcc−Vtsg] (where Vtsg is the threshold voltage of the select gate transistor) and then enters a floating state. Subsequently, one control gate line in the selected NAND cell changes in potential from 0 V to Vpp (=20 V or so, which is a programming high voltage), while the other control gate line in the selected NAND cell changes in potential from 0 V to Vmg (=10 V or so, which is an intermediate voltage).
Because the selected NAND cell connected to the “0” data programming bit line has its channel portion fixed at 0 V, it has a large potential difference (=20 V or so) between its selected memory cell's control gate line (=Vpp potential) and its channel portion (=0 V), thus causing electrons to be injected from the channel portion to the floating gate. Accordingly, the threshold voltage of that selected memory cell shifts to the positive direction, thus completing programming of data “0”.
The selected NAND cell connected to the “1” data programming bit line, on the other hand, has its channel portion in a floating state, so that the influence of the capacitive coupling between its control gate line and its channel portion raises the voltage of the control gate line (0 V>Vpp, Vmg), which in turn raises the potential of the channel portion from a [Vcc−Vtsg] potential to Vmch (=8 V or so) with that channel portion as held in the floating state. In this case, since the potential difference between the control gate line (=Vpp potential) and the channel portion (=Vmch) of the selected memory cell in the selected NAND cell is a relatively low value of 12 V or so, thus avoiding the electron injection. Therefore, the threshold voltage of the selected memory cell is held unchanged at the negative value.
Data erase is carried out to all of the memory cells in the selected NAND cell block at the same time. That is, 0 V is applied to all the control gate lines in the selected NAND cell block, while a high voltage of 20 V or so is applied to the bit lines, source lines, p-type well regions (or p-type semiconductor substrate), and the control gate lines and all the select gate lines in the non-selected NAND cell blocks. Thus, in all the memory cells in the selected NAND cell block, the electrons in the floating gate are emitted to the p-type well (or p-type semiconductor substrate), thus shifting the threshold voltage to the negative direction.
Data reading, on the other hand, is carried out by applying 0 V to the control gate line in the selected memory cell and a reading intermediate voltage Vread (4 V or so) to the control gate line and the select gate line of the other memory cells to detect whether a current flows through that selected memory cell.
As may be obvious from the above description, to write data into a NAND cell-type EEPROM, it is necessary to apply voltages higher than the power supply voltage, i.e., Vpp (20 V or so) to the selected control gate line in the selected block and Vmg (10 V or so) to the non-selected control gate line in that selected block.
To transfer such high voltages Vpp and Vmg to the memory cell, the conventional NAND-type EEPROM includes a row decoder circuit including a voltage conversion circuit which converts the power supply voltage to such high voltages (see, for example, U.S. Pat. No. 6,621,735). The voltage conversion circuit needs to include a PMOS transistor of a high withstand voltage.